Embedded Systems
Microcontroller firmware, IoT devices, FPGA digital logic design, and hardware-software integration.
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Two Worlds, One Frame: Synchronizing Parallel Reality State Without Tearing the Simulation Apart
Imagine a game where a door unlocked in Reality A must also appear unlocked in Reality B — but the key that opened it only exists in Reality A's inventory, and the agent who picked it up is standing in a completely different position in Reality B. Some state is shared. Some state is independent. And when the player presses one button to switch realities, the entire world must pivot atomically — no system should ever observe a half-switched state during a frame.
10 Milliseconds or Failure: Architecting a Real-Time Sensor Pipeline Across Two Threads Without Locking Up the UI
A deep dive into the engineering of a real-time IMU processing pipeline that runs on a worker thread while communicating with a Qt Quick UI on the main thread. Learn how to use `std::atomic` for lock-free shutdown signaling, Qt's queued signals for cross-thread communication, and self-correcting timing loops to maintain a 100 Hz sample rate without ever blocking the UI thread.
Your Gyroscope Is a Liar: Using a Kalman Filter to Fuse Contradictory Sensors Into Trustworthy Orientation
A deep dive into the engineering of a real-time Kalman filter for fusing accelerometer and gyroscope data on an embedded system, including a custom matrix library, C++17 optimizations, and practical tuning advice for sensor noise.
Your Sensor Remembers Nothing: Building a Fixed-Memory Ring Buffer to Give Hardware a Short-Term History
A deep dive into the architecture and engineering of a privacy-first mobile mindfulness coach that runs entirely on-device using React Native and Google MediaPipe's on-device LLM capabilities.
The Instruction That Needs an Answer Before the Question Is Asked
A detailed walkthrough of the `bypass` module in this Wordle project — a combinational forwarding network that detects and resolves data hazards in a five-stage RISC pipeline, ensuring correct execution without stalling for register-to-register dependencies.
How a 25 MHz Clock Becomes 307,200 Pixels on a Screen
A deep dive into the `simple_480p` VGA timing generator, revealing how two counters and a handful of comparators produce the exact sequence of signals required to drive a 640×480 display at 60 Hz — all from first principles in Verilog.